On the Realization of Online Ternary Testable Circuit

Ternary Reversible logic got the attention in the recent years for its applications in different sections of Reversible Logic Synthesis. Designing online testable circuits are also considered as the prominent field of research in this domain. This paper presents a novel idea of Online Testable Ternary Reversible Circuits design, where architecture is capable of testing reversible ternary network in real-time (online). The error detection unit, a component of the proposed design, is also designed with reversible gates, for which the entire circuit is considered reversible. The evaluation of the proposed design is carried out with example circuits in terms of well-know design parameters to show the effectiveness and compactness of the circuit.